1. Field of the Invention
The present invention relates to a solid-state image pickup element and an image pickup apparatus, such as a camera, including the same.
2. Description of the Related Art
A configuration including a photodiode utilizing a pn junction of a semiconductor as a photoelectric conversion element is known for a solid-state image pickup element (image sensor) using a semiconductor.
Such a solid-state image pickup element is mounted to many apparatuses such as a digital camera, a video camera, a monitoring camera, a copying machine, and a facsimile.
Also, a so-called CMOS (complementary metal oxide semiconductor) type solid-state image pickup element which is manufactured in a CMOS process, including a peripheral circuit is used as such a solid-state image pickup element in many cases.
FIG. 20 is a schematic block diagram showing an example of a configuration of a CMOS type solid-state image pickup element.
As known in FIG. 20, the CMOS type solid-state image pickup element includes plural pixels 51 which are disposed in a matrix and each of which carries out photoelectric conversion, vertical signal lines 52 through which signals are taken out from the pixels 51, respectively, a vertical selection circuit 53, a horizontal selection/signal processing circuit 54, and an output circuit 55 on the same semiconductor substrate. In FIG. 20, reference numeral 56 designates an image capturing area.
FIG. 21 is a circuit diagram showing a configuration of a unit pixel of the CMOS type solid-state image pickup element shown in FIG. 20.
As shown in FIG. 21, the unit pixel includes a photodiode PD serving as a photoelectric conversion element, a transfer transistor 61, a reset transistor 62, an amplification transistor 63, a selection transistor 64, a vertical signal line 65, and a floating diffusion area CFD.
The reset transistor 62, the transfer transistor 61, and the selection transistor 64 are connected to a reset line RST, a transfer line TX, and a horizontal selection line SEL, respectively, and are driven in accordance with pulse signals from the vertical selection circuit 53 shown in FIG. 20.
The photodiode PD is connected in one end thereof to the ground, and converts a light made incident thereto into electrons (or holes) by photoelectric conversion to accumulate therein the resulting electric charges (electrons or holes). The other end of the photodiode PD is connected to the floating diffusion area CFD through the transfer transistor 61. Thus, by turning ON the transfer line TX, the electric charges are transferred from the photodiode PD to the floating diffusion area CFD.
One end of the floating diffusion area CFD is connected to a gate electrode of the amplification transistor 63, and is also connected to the vertical signal line 65 through the selection transistor 64. Plural unit pixels are connected to the vertical signal line 65. Thus, the selection transistor 65 connected to a certain specific vertical signal line 65 is turned ON, whereby a signal from a desired photodiode PD is outputted. The vertical signal line 65 is connected to a transistor (constant current source) 66 biased by a constant voltage and composes a so-called source follower circuit in combination with the amplification transistor 63.
In addition, FIG. 22 shows an example of a planar layout of the unit pixel of the CMOS type solid-state image pickup element.
For isolation of the photodiode PD and the transistors, a p-type well region (not shown) is provided in the circumference of the photodiode PD and the transistors.
Although heretofore, a well constant is provided only in the circumference of the pixel area, in this example, the contact is provided in each of the pixels along with the multiple pixel promotion. That is to say, for the purpose of connecting a metallic wire 69 and a p-type well region to each other, a well contact 68 is provided in a top left corner of a photoelectric conversion area 67 including a photodiode.
Here, FIG. 23 is a cross sectional view taken on line X-X′ of FIG. 22 in the case where isolation between elements is carried out by an insulator and a p-type region. An upper metallic wiring layer is omitted in illustration in FIG. 23.
Although the isolation between the elements is basically carried out by an insulator 76, normally, a p-type region 77 is formed under the insulator 76. The p-type region 77 is connected together with a p+-type region 74 on the surface of the photodiode to the well contact 68.
Although in FIG. 23, the inter-element isolation is carried out by both the isolation 76 and the p-type region 77, as with a cross sectional view shown in FIG. 24 similar to FIG. 23, the inter-element isolation region can be formed by only the p-type region 77.
In this case as well, similarly to the case of FIG. 23, both the p-type region 77 for the inter-element isolation, and the p+-type region 74 on the photodiode are connected to the well contact 68.
As shown in FIGS. 23 and 24, the p-type region 77 for the inter-element isolation is connected to the well contact 68. In this structure, however, there is known a problem that electrons e− as minority carriers are injected from the well contact 68 to the p-type region 77. This problem is described in Japanese Patent Laid-Open No. 2006-32385.
That is to say, this problem is such that as indicated by arrows in FIGS. 23 and 24, respectively, the injected electrons e− are diffused within the p-type region 77 to flow into the n-type region 73 in which the electrons generated in the photodiode by the photoelectric conversion are accumulated, and turn into a dark current, thereby deteriorating the image quality.
Now, as shown in a circuit diagram of FIG. 25, a so-called sharing pixel configuration in which the floating diffusion area CFD, the amplification transistor 63, and the selection transistor 64 are shared among plural photodiodes is generally known.
In the circuit configuration shown in FIG. 21, the configuration is adopted such that one photodiode PD is connected to one amplification transistor 63. On the other hand, in the circuit configuration shown in FIG. 25, a configuration is adopted such that four photodiodes PD1, PD2, PD3, and PD4 are connected to one amplification transistor 63. That is to say, the amplification transistor 63 and the like are shared among four pixels. It is noted that the transfer transistor 61 is provided every pixel.